Thin film transistors (TFTs) are gaining acceptance in the semiconductor industry. In fact, TFT devices have already found application in both flat panel displays and in static memory devices. In the case of static memory devices, complementary metal oxide semiconductor (CMOS) and bipolar metal oxide semiconductor (BiCMOS) static random access memories (SRAMs) have in the past predominantly used polysilicon resistor load devices. The semiconductor industry's continual drive toward higher density SRAMs, however, makes the replacement of these traditional polysilicon resistor load devices with TFT devices very desirable. Both SRAMs and flat panel displays require well-behaved TFT devices that exhibit low leakage currents and high on/off current ratios. In addition, high density SRAMs require TFT devices that are compatible with small memory cell sizes.
The fabrication of reliable transistors with well-behaved electrical characteristics generally requires tile source and drain regions of the transistor to be self-aligned to the gate. This allows the transistor channel length to be manufacturably fabricated because the source and drain regions are reproducibly self-aligned to the transistor channel region. The formation of TFT devices with self-aligned source and drain regions, however, has been difficult to achieve. Several different TFT devices such as, vertical, over-gated, and under-gated have been proposed in the past. Of these devices, however, only the over-gated TFT can be easily fabricated with self-aligned source and drain regions. Unfortunately, the utilization of over-gated TFTs in high density SRAMs is limited. Over-gated TFTs require an additional polysilicon gate electrode which must be electrically contacted to the control electrode of the latch transistor. The area required for laying out the polysilicon gate electrode, and the latch transistor contact, is substantial and thus limits the memory cell size that can be achieved with over-gated TFTs. Accordingly, a need exists for a TFT device, which is compatible with high device density requirements, and which has self-aligned source and drain regions.